Integration scheme for reducing border region morphology in hybrid orientation technology (hot) using direct silicon bonded (dsb) substrates

ABSTRACT

Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming ( 100 )-oriented silicon regions for NMOS and ( 110 ) regions for PMOS. Boundary regions between ( 100 ) and ( 110 ) regions must be sufficiently narrow to support high gate densities and SRAM cells appropriate for the technology node. This invention provides a method of forming an integrated circuit (IC) substrate containing regions with two different silicon crystal lattice orientations. Starting with a ( 110 ) direct silicon bonded (DSB) layer on a ( 100 ) substrate, regions in the DSB layer are amorphized and recrystallized on a ( 100 ) orientation by solid phase epitaxy (SPE). Lateral templating by the DSB layer is reduced by amorphization of the upper portion of the ( 110 ) regions through a partially absorbing amorphization hard mask. Boundary morphology is less than 40 nanometers wide. An integrated circuit formed with the inventive method is also disclosed.

This application is a divisional of and incorporates by reference U.S.non-provisional patent application Ser. No. 12/343,743, filed Dec. 24,2008, entitled “INTEGRATION SCHEME FOR REDUCING BORDER REGION MORPHOLOGYIN HYBRID ORIENTATION TECHNOLOGY (HOT) USING DIRECT SILICON BONDED (DSB)SUBSTRATES”, which claims the benefit of and incorporates by referenceU.S. provisional application No. 61/016,545, filed Dec. 24, 2007,entitled “INTEGRATION SCHEME FOR REDUCING BORDER REGION MORPHOLOGY INHYBRID ORIENTATION TECHNOLOGY (HOT) USING DIRECT SILICON BONDED (DSB)SUBSTRATES”.

FIELD OF THE INVENTION

This invention relates to the field of integrated circuits. Moreparticularly, this invention relates to methods of fabricatingintegrated circuits containing regions with different crystalorientations.

BACKGROUND OF THE INVENTION

It is well recognized that increasing the mobility of charge carriers inmetal oxide semiconductor (MOS) transistors in integrated circuits (ICs)improves the operating speed of ICs. There are several techniques usedin advanced ICs to increase the mobilities of electrons and holes insilicon n-channel MOS (NMOS) and p-channel (PMOS) transistors, includingorienting the silicon substrate to take advantage of the fact thatcarrier mobility varies depending on the orientation of the crystallattice in the MOS transistor channel. Electrons have maximum mobilityin (100)-oriented silicon when the NMOS transistor is aligned on a [110]axis, that is, when the electron movement in the NMOS transistor channelis along a [110] direction. Holes have maximum mobility in(110)-oriented silicon when the PMOS transistor is aligned on a [110]axis. To maximize the mobilities of electrons and holes in the same ICrequires regions with (100)-oriented silicon and (110)-oriented siliconin the substrate, known as hybrid orientation technology (HOT). Knownmethods of HOT include amorphization and templated recrystallization(ATR). In one variation of ATR, in which recrystallization is performedbefore a shallow trench isolation (STI) process, discontinuities anddefects (morphology) are introduced in a region approximately 100nanometers wide at the lateral boundaries between (100)-oriented and(110)-oriented silicon. The morphology region is not suitable for MOStransistors, proscribing conventional ATR for use in circuits requiringhigh transistor density, such as SRAMs or logic gates. The morphologyregion also imposes unacceptable limits on transistor scaling. Inanother variation of ATR, in which recrystallization is performed afteran STI process, stable defects are introduced at the STI boundarieswhich require anneals over 1250 C to be eliminated. Such anneals areincompatible with maintaining dimensional integrity of the substraterequired for deep submicron lithography used in the 65 nanometertechnology node and more advanced nodes.

SUMMARY OF THE INVENTION

This Summary is provided to comply with 37 C.F.R. §1.73, requiring asummary of the invention briefly indicating the nature and substance ofthe invention. It is submitted with the understanding that it will notbe used to interpret or limit the scope or meaning of the claims.

This invention provides a method of forming an integrated circuit (IC)which has two types of regions with different silicon crystal latticeorientations, (100)-oriented silicon and (110)-oriented silicon, forforming transistors, in order to optimize performance parameters, suchas carrier mobility, for NMOS and PMOS transistors separately. Themethod starts with a single crystal substrate of (100)-oriented siliconwith a directly bonded silicon (DSB) layer of (110)-oriented siliconformed on the top surface of the substrate. A partially absorbingamorphization hard mask layer is formed over regions for PMOStransistors, followed by an amorphizing ion implant which completelyamorphizes the (110)-oriented silicon layer in NMOS regions andamorphizes the silicon in the top portion of the DSB layer under thepartially absorbing amorphization hard mask layer. A solid phaseepitaxial (SPE) process is performed in which (100)-oriented silicon isformed in the NMOS regions using the (100)-oriented silicon in the wafersubstrate for a seed layer. Lateral spread of the boundary regionbetween the DSB layer and the SPE layer is reduced by the presence ofthe amorphized silicon in the PMOS regions, which recrystallizes to form(110)-oriented silicon using the DSB silicon for a seed layer, and doesnot template (110)-oriented recrystallization into the NMOS regions. Anintegrated circuit formed using the inventive method is also disclosed.

DESCRIPTION OF THE VIEWS OF THE DRAWING

FIG. 1A through FIG. 1F are cross-sections of an integrated circuitduring fabrication of NMOS and PMOS transistors according to anembodiment of the instant invention.

DETAILED DESCRIPTION

The present invention is described with reference to the attachedfigures, wherein like reference numerals are used throughout the figuresto designate similar or equivalent elements. The figures are not drawnto scale and they are provided merely to illustrate the invention.Several aspects of the invention are described below with reference toexample applications for illustration. It should be understood thatnumerous specific details, relationships, and methods are set forth toprovide a full understanding of the invention. One skilled in therelevant art, however, will readily recognize that the invention can bepracticed without one or more of the specific details or with othermethods. In other instances, well-known structures or operations are notshown in detail to avoid obscuring the invention. The present inventionis not limited by the illustrated ordering of acts or events, as someacts may occur in different orders and/or concurrently with other actsor events. Furthermore, not all illustrated acts or events are requiredto implement a methodology in accordance with the present invention.

To assist readability of this disclosure, silicon crystal orientationswill be referred to using the nomenclature “(100)-oriented silicon” or“(110)-oriented silicon” to avoid confusion with numerical designationsof elements in the figures attached to this disclosure, for example “thefield oxide (100).”

The instant invention addresses the need for a robust and cost effectivemethod of fabricating integrated circuits (ICs) with regions ofdifferent crystal lattice orientation, known as hybrid orientationtechnology (HOT), by providing a direct silicon bonded (DSB) substratein which a layer of (110)-oriented silicon is attached to a(100)-oriented silicon wafer substrate, forming a partially absorbingamorphization hard mask layer over regions for PMOS transistors,performing an amorphizing ion implant which completely amorphizes the(110)-oriented silicon layer in NMOS regions and partially amorphizesthe silicon at the surface in the PMOS regions, and recrystallizing theamorphous silicon in a solid phase epitaxial (SPE) process in which(100)-oriented silicon is formed in the NMOS regions using the(100)-oriented silicon in the wafer substrate for a seed layer. Lateralspread of the morphology region is reduced by the presence of thepartially amorphized silicon in the PMOS regions, which recrystallizesto form (110)-oriented silicon using the DSB silicon for a seed layer,and does not template (110)-oriented recrystallization into the NMOSregions.

FIG. 1A through FIG. 1F are cross-sections of an integrated circuitduring fabrication of NMOS and PMOS transistors according to anembodiment of the instant invention.

FIG. 1A is a cross-section of a hybrid substrate (100), which includes asubstrate (102) of (100)-oriented silicon, typically p-type with aresistivity of 1 to 100 ohm-cm, and a DSB layer (104) of (110)-orientedsilicon, typically p-type with an electrical resistivity of 1 to 100ohm-cm, on a top surface of the substrate (102). The DSB layer (104) is100 to 250 nanometers thick. In one embodiment, the DSB layer (104) issubstantially undoped. In a further embodiment, germanium or carbonatoms may be added to change a material property, such as increasestress in the DSB layer (104) which can be advantageous by increasingtransistor on-state drive current. A partially absorbing amorphizationhard mask layer (106), of silicon dioxide, silicon nitride, siliconoxy-nitride, or a combination of these materials, approximatelyone-third as thick as the DSB layer (104), is formed on a top surface ofthe DSB layer (104). A photoresist pattern (108) is formed on a topsurface of the amorphization hard mask layer (106), covering a p-channelMOS transistor (PMOS) region (110) and exposing an n-channel MOStransistor (NMOS) region (112).

FIG. 1B depicts the IC (100) after removal of the amorphization hardmask layer (106) in the NMOS region (112) by known etching techniques,commonly plasma etching using fluorine containing gases. After etchingthe amorphization hard mask layer (106), the photoresist and etchresidue are removed, typically by ashing in an oxygen-containing plasmafollowed by immersion in a mixture of sulfuric acid and peroxide.

Referring to FIG. 1C, fabrication of the IC (100) continues with anamorphization ion implant process. Ions (114), preferably silicon orgermanium, are ion implanted into the IC (100) at a dose and an energysufficient to form an amorphous silicon region (116) in the NMOS region(112) from the top surface of the DSB layer to a depth greater than thethickness of the DSB layer. For example, a silicon ion implant with adose of 2.5·10¹⁵ cm⁻² at an energy of 70 keV is sufficient to amorphize165 nanometers of crystalline silicon, and thus would be appropriate fora 150 nanometer thick DSB layer. The amorphization hard mask (106)blocks enough of the implanted ions (114) that the crystalline siliconin the DSB layer (104) in the PMOS region (110) is amorphized from thetop surface of the DSB layer to a depth approximately two-thirds of theDSB layer thickness, forming a shallower amorphous silicon region (118)in the PMOS region (110). The thickness of the amorphization hard mask(106) is set by a desired depth of the amorphous region (118) in thePMOS region (110) and by the amorphization ion implant dose and energy.

FIG. 1D depicts the IC (100) after removal of the amorphization hardmask layer, deposition of a recrystallization oxide cap layer (120), anda subsequent recrystallization process known as solid phase epitaxy(SPE) in which the amorphous silicon in the NMOS region (112) isrecrystallized into a (100)-oriented SPE layer (122), and the amorphoussilicon in the PMOS region (110) is recrystallized into a (100)-orientedlattice. The recrystallization oxide cap layer (120) is typically 10 to30 nanometers of silicon dioxide deposited by plasma enhanced chemicalvapor deposition (PECVD). The recrystallization oxide cap layer (120)must be formed at a low temperature so that recrystallization does notcommence to any substantial degree and must also bond well enough to thesilicon at the top surfaces of the amorphous layers in the NMOS regionand the PMOS region so that the recrystallized silicon in supports MOStransistors with performance equivalent to bulk crystalline silicon. Anydielectric layer or layers which meet these two requirements is withinthe scope of the instant invention. In the NMOS region (112), the(100)-oriented substrate (102) provides the seed layer forrecrystallization, and recrystallization is accomplished so that thereare substantially no discontinuities or defects at the original boundary(124) between the amorphous region and the substrate. In the PMOS region(110), the (110)-oriented silicon in a bottom region of the DSB layer(104) provides the seed layer for recrystallization. Thus, it isimportant for the amorphization hard mask to block enough of theamorphization ion implant to leave sufficient (110)-oriented crystallinesilicon in the DSB layer to provide a seed layer for recrystallizationof the amorphous layer into a (110)-oriented lattice. A typicalrecrystallization process includes a first anneal at 600 C for 2 hoursin a nitrogen ambient followed by a second anneal at 1050 C for 2 hoursin a nitrogen ambient. The lateral boundary (126) between the(110)-oriented DSB layer and the (100)-oriented SPE layer issubstantially vertical, due to a reduction in lateral growth of(110)-oriented silicon because of the amorphous condition of the siliconin the upper region of the DSB layer during the SPE process. A width(128) of the boundary region (126) including discontinuities and defectsis less than 40 nanometers, which is advantageous because NMOS and PMOStransistors can be positioned closer together, resulting in moreefficient IC layouts and lower manufacturing costs per IC, as well asenabling transistor scaling for subsequent integrated circuitfabrication nodes.

Referring to FIG. 1E, fabrication of the IC (100) continues with growthof an SPE sacrificial oxide layer, not shown in FIG. 1E, typically 5 to15 nanometers of thermal oxide, to consume defects at the top surfacesof the substrate in the PMOS region and the NMOS region. Regions offield oxide (132) are formed by a shallow trench isolation (STI) processsequence, in which trenches, commonly 200 to 500 nanometers deep, areetched into the IC, electrically passivated, commonly by growing athermal oxide layer on sidewalls of the trenches, and filled withinsulating material, typically silicon dioxide, commonly by a highdensity plasma (HDP) process or a high aspect ratio process (HARP). In apreferred embodiment, the SPE sacrificial oxide layer is reused as asacrificial pad oxide for the STI process. This is advantageous becausereuse of the sacrificial oxide layer reduces an offset between the topsurface of the NMOS region and the top surface of the PMOS region, whichresults from a difference in oxidation rates between (110) orientedsilicon and (110) oriented silicon. The lateral boundary region betweenthe DSB layer (104) and the SPE layer (122) is occupied by a field oxide(132) region, providing an electrically passivated lateral boundary forthe (100)-oriented layer (122) and the (110)-oriented layer (104). Afterformation of the field oxide (132), a sacrificial oxide layer (130) isgrown on the top surfaces of the NMOS region and the PMOS region toprotect the surfaces during a subsequent well formation processsequence.

Fabrication of the IC on the HOT substrate prepared according to theinstant invention is depicted in FIG. 1F. A p-type well (134) is formedin the regions defined for NMOS transistors by known methods of ionimplanting p-type dopants such as boron, BF2 or indium, commonly inseveral step with doses from 1·10¹⁰ to 1·10¹⁴ cm⁻² at energies from 2keV to 200 keV. Similarly, an n-type well (136) is formed in regionsdefined for PMOS transistors by known methods of ion implanting n-typedopants such as phosphorus, arsenic or antimony, commonly in severalstep with doses from 1·10¹⁰ to 1·10¹⁴ cm⁻² at energies from 1 keV to 500keV. Formation of an NMOS transistor proceeds with formation of an NMOSgate dielectric layer (138), typically silicon dioxide, nitrogen dopedsilicon dioxide, silicon oxy-nitride, hafnium oxide, layers of silicondioxide and silicon nitride, or other insulating material, on a topsurface of the p-type well (134), followed by formation of an NMOS gate(140), typically polycrystalline silicon, on a top surface of the NMOSgate dielectric layer (138), with NLDD offset spacers (142), typicallyone or more layers of silicon dioxide and/or silicon nitride formed byplasma etch, with a width from 1 to 30 nanometers, on lateral surfacesof the NMOS gate (140). N-type medium doped drain regions (NLDD) (144)are formed in the p-type well (134) adjacent to the NMOS gate (140) byion implantation of n-type dopants such as phosphorus, arsenic and/orantimony, commonly in several step with doses from 1·10¹³ to 1·10¹⁶ cm⁻²at energies from 1 keV to 10 keV. Typical depths of n-type dopants inthe NLDD (144) range from 5 to 50 nanometers. Following ion implantationof n-type dopants into the NLDD (144), NMOS gate sidewall spacers (146)are formed on lateral surfaces of the NLDD offset spacers (142),commonly by deposition of layers of silicon dioxide and silicon nitridespacer material followed by anisotropic etchback to remove spacermaterial from horizontal surfaces of the IC (100). Typical NMOS gatesidewall spacer widths range from 3 to 100 nanometers. Followingformation of the NMOS gate sidewall spacers (146), NMOS source and drainregions (NSD) (148) are formed by in the p-type well (134) adjacent tothe NMOS gate sidewall spacers (146) by ion implantation of n-typedopants such as phosphorus, arsenic and/or antimony, commonly in severalstep with doses from 1·10¹⁴ to 1·10¹⁶ cm⁻² at energies from 3 keV to 50keV. Typical depths of n-type dopants in the NSD (148) range from 10 to250 nanometers. In a preferred embodiment, the thickness of the DSBlayer (104) and the depth of the amorphous region formed by theamorphization ion implant are set so that the interface (124) betweenthe substrate (102) and the SPE layer (122) is below a space chargeregion of the NSD (148). Anneals may be performed after the NLDD ionimplants and the NSD ion implants to repair damage to the siliconlattice of the SPE layer (122) by the ion implantation processes. Thep-type well (134), NMOS gate dielectric layer (138), NMOS gate (140),NLDD offset spacers (142), NLDD (144), NMOS gate sidewall spacers (146)and NSD (148) form an NMOS transistor (110). Layers of metal silicide(150) may be formed on top surfaces of the NSD (148) to decreaseelectrical resistance of contacts made to the NSD (148).

Still referring to FIG. 1F, fabrication of the integrated circuit (100)continues with formation of a PMOS transistor. A PMOS gate dielectriclayer (152), typically silicon dioxide, nitrogen doped silicon dioxide,silicon oxy-nitride, hafnium oxide, layers of silicon dioxide andsilicon nitride, or other insulating material, on a top surface of then-type well (136), followed by formation of an PMOS gate (154),typically polycrystalline silicon, on a top surface of the PMOS gatedielectric layer (152), with PLDD offset spacers (156), typically one ormore layers of silicon dioxide and/or silicon nitride formed by plasmaetch, with a width from 1 to 30 nanometers, on lateral surfaces of thePMOS gate (154). P-type medium doped drain regions (PLDD) (158) areformed in the n-type well (136) adjacent to the PMOS gate (154) by ionimplantation of p-type dopants such as boron, BF2 and/or gallium,commonly in several step with doses from 1·10¹³ to 1·10¹⁶ cm⁻² atenergies from 0.3 keV to 10 keV. Typical depths of p-type dopants in thePLDD (158) range from 5 to 50 nanometers. Following ion implantation ofp-type dopants into the PLDD (158), PMOS gate sidewall spacers (160) areformed on lateral surfaces of the PLDD offset spacers (156), commonly bydeposition of layers of silicon dioxide and silicon nitride spacermaterial followed by anisotropic etchback to remove spacer material fromhorizontal surfaces of the IC (100). Typical PMOS gate sidewall spacerwidths range from 3 to 100 nanometers. Following formation of the PMOSgate sidewall spacers (160), PMOS source and drain regions (PSD) (162)are formed by in the n-type well (136) adjacent to the PMOS gatesidewall spacers (160) by ion implantation of p-type dopants such asboron, BF2 and/or gallium, commonly in several step with doses from1·10¹⁴ to 1·10¹⁶ cm⁻² at energies from 3 keV to 50 keV. Typical depthsof p-type dopants in the PSD (162) range from 10 to 250 nanometers. In apreferred embodiment, the thickness of the DSB layer (104) is adjustedso that an interface between the substrate (102) and the DSB layer (104)is below a space charge region of the PSD (162). Anneals may beperformed after the PLDD ion implants and the PSD ion implants to repairdamage to the silicon lattice of the DSB layer (104) by the ionimplantation processes. The n-type well (136), PMOS gate dielectriclayer (152), PMOS gate (154), PLDD offset spacers (156), PLDD (158),PMOS gate sidewall spacers (160) and PSD (162) form a PMOS transistor(110). Layers of metal silicide (164) may be formed on top surfaces ofthe PSD (158) to decrease electrical resistance of contacts made to thePSD (158).

Still referring to FIG. 1F, fabrication of the IC (100) continues withformation of a pre-metal dielectric liner (PMD liner) (166), typicallysilicon nitride, 2 to 100 nanometer thick, on top surfaces of the NMOStransistor (112), the PMOS transistor (110) and the field oxide (132).In some embodiments, a dual stress layer (DSL) PMD liner is formed,which applies different levels of stress to different components in theIC, such as compressive stress on PMOS transistors and tensile stress onNMOS transistors. A pre-metal dielectric layer (PMD) (168), typicallysilicon dioxide, 152 to 1000 nanometers thick, is formed on a topsurface of the PMD liner (166). Contacts (170) to the NSD (162) and PSD(148) are formed by etching holes in the PMD (168) and PMD liner (166)to expose portions of the top surfaces of the NSD (162) and PSD (148),and filling the holes with metals, typically tungsten. The contacts(170) allow electrical connections to be made to the NMOS and PMOStransistors (112, 110).

The formation of the NMOS transistor (112) in the SPE layer (122) isadvantageous because the (100)-oriented silicon in the SPE layermaximizes the electron mobility in an NMOS channel, and thus maximizesthe NMOS on-state drive current. The formation of the PMOS transistor(110) in the DSB layer is advantageous because the (110)-orientedsilicon in the DSB layer maximizes the hole mobility in a PMOS channel,and thus maximizes the PMOS on-state drive current.

It is within the scope of this invention to exchange the silicon crystallattice orientations of the substrate, DSB layer and SPE layer, and forma p-type well and an NMOS transistor in the DSB layer and an n-type welland a PMOS transistor in the SPE layer, and realize the same advantageswith respect to maximization of on-state drive currents explained above.

The silicon crystal lattice orientations of the substrate and DSB layermay be altered from the (100) and (110) orientations described in theembodiments above, to suit a particular application, for example aradiation resistant IC, and still fall within the scope of thisinvention. This invention generally discloses a method to obtain regionswith two silicon crystal lattice orientations for electronic components,and is not limited to the (100) and (110) orientations, nor totransistors as the only components formed in the DSB and SPE layers.

Those skilled in the art to which the invention relates will appreciatethat the described implementations are merely illustrative exampleembodiments, and that there are many other embodiments and variations ofembodiments that can be implemented within the scope of the claimedinvention.

1. An integrated circuit (IC) comprising: provided a single crystalsubstrate, comprised of silicon with a first crystal latticeorientation; a layer of directly bonded silicon (DSB) with a secondcrystal lattice orientation formed on a top surface of said singlecrystal substrate; a region with said first crystal lattice orientationformed in said DSB layer and connecting with said top surface of saidsingle crystal substrate, formed by solid phase epitaxy (SPE); a regionof field oxide formed at a lateral boundary between said region withsaid first crystal lattice orientation and said region with said secondcrystal lattice orientation; a first well of a first electrical typeformed in said region with said first crystal lattice orientation by ionimplanting a first set of dopants of said first electrical type; asecond well of a second electrical type formed in said regions with saidsecond crystal lattice orientation by ion implanting a second set ofdopants of said second electrical type; a first MOS transistor formed insaid first well, further comprising: a first gate dielectric layerformed on a top surface of said first well; a first gate formed on a topsurface of said first type of gate dielectric layer; a first set of LDDoffset spacers formed on lateral surfaces of said first type of gate; afirst set of LDD regions of said second electrical type formed in saidfirst type of well adjacent to said first type of gate by ion implantinga second set of said second type of dopants; a first set of gatesidewall spacers formed on lateral surfaces of said first type of LDDoffset spacers; and a first set of SD regions of said second electricaltype formed in said first type of well adjacent to said first type ofgate sidewall spacers by ion implanting a third set of said second typeof dopants; a second MOS transistor formed in said second well by aprocess further comprising the steps of: a second gate dielectric layerformed on a top surface of said second well; a second gate formed on atop surface of said second type of gate dielectric layer; a second setof LDD offset spacers formed on lateral surfaces of said second type ofgate; a second set of LDD regions of said first electrical type formedin said second type of well adjacent to said second type of gate by ionimplanting a second set of said first type of dopants; a second set ofgate sidewall spacers formed on lateral surfaces of said second type ofLDD offset spacers; and a second set of SD regions of said firstelectrical type formed in said second type of well adjacent to saidsecond type of gate sidewall spacers by ion implanting a third set ofsaid first type of dopants; a PMD liner formed on top surfaces of saidfirst type of transistor, said second type of transistor and said fieldoxide region; a PMD layer formed on a top surface of said PMD liner; andcontacts formed in said PMD layer and said PMD liner to make electricalconnections to said first type of SD regions and said second type of SDregions.
 2. The IC of claim 1, in which crystal lattice discontinuitiesat a lateral boundary between regions defined for said first crystallattice orientation and regions defined for said second crystal latticeorientation are contained in a zone less then 40 nanometers wide.
 3. TheIC of claim 1, in which crystal lattice discontinuities at a lateralboundary between regions defined for said first crystal latticeorientation and regions defined for said second crystal latticeorientation are contained in a zone less then 30 nanometers wide.
 4. TheIC of claim 3, in which: said first crystal lattice orientation is a(100) orientation; said second crystal lattice orientation is a (110)orientation; said first electrical type is p-type; said secondelectrical type is n-type; said first MOS transistor is an n-channel MOStransistor; and said second MOS transistor is a p-channel MOStransistor.
 5. The IC of claim 4, in which a thickness of said DSB layeris between 100 and 250 nanometers.